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document number: MMA7450L rev 0, 6/2007 freescale semiconductor technical data this document contains certai n information on a new product. specifications and information herein are subject to change without notice. ? freescale semiconductor, in c., 2007. all rights reserved. 2g/4g/8g three axis low-g digital output accelerometer the MMA7450L is a digital output (i 2 c/spi), low power, low profile capacitive micromachined accelerometer featuring signal conditioning, a low pass filter, temperature compensation, se lf test, configurable to detect 0g through interrupt pins (int1 or int2), and pulse (click) detect for quick motion detection. the 0g offset can be cust omer calibrated using assigned 0g registers and g-select which allows fo r command selection for 3 sensitivities (2g/4g/8g). zero-g offset and sensitivity are factory set and require no external devices. the MMA7450L includes a standby mode that makes it ideal for handheld battery powered electronics. features ? digital output (i 2 c/spi) - 10-bit at 8g mode ? 3mm x 5mm x 0.8mm lga-14 package ? low current consumption: 400 a ? sleep mode: 5 a ? low voltage operation: 2.4 v ? 3.6 v ? customer assigned registers for offset calibration ? programmable threshold interrupt output ? level/pulse detection for motion reco gnition (shock, vibration, freefall) ? click detection for single or double click recognition ? high sensitivity (64 lsb/g @ 2g and @ 8g in 10-bit mode) ? selectable sensitivity (2g, 4g, 8g) ? self test for x-axis ? robust design, high shocks survivability (10,000 g) ? rohs compliant ? environmentally preferred product ? low cost typical applications ? cell phone/pmp/pda: image stability, text scroll, motion dialing, e-compass, tap to mute ? hdd: freefall detection ? laptop pc: freefall detection, anti-theft ? navigation and dead reckoning: position detection, pedometer ? e-compass tilt compensation ? 3d gaming: tilt and motion sensing, event recorder ordering information part number temperature range package shipping MMA7450Lt ?20 to +65c lga-14 tray MMA7450Lr1 ?20 to +65c lga-14 tape & reel (7? reel) MMA7450Lr2 ?20 to +65c lga-14 tape & reel (13? reel) MMA7450L MMA7450L: xyz axis accelerometer 2g/4g/8g 14 lead lga case 1935-01 bottom view figure 1. pin connections top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 avdd gnd dvdd_io slc/spc cs int1/drdy int2 n/c sdo sda/sdi/sdo n/c n/c n/c gnd
sensors 2 freescale semiconductor MMA7450L figure 2. simplified accelerometer functional block diagram electro static discharge (esd) warning: this device is se nsitive to electrostatic discharge. although the freescale accelerometer contains internal 2000v esd protection circuitry, extra precaution must be taken by the user to protect the chip from esd. a charge of over 2000 volts can accumulate on the human body or associated test equipment. a charge of this magnitude can alter the performance or cause failure of the chip. when handling the accelerometer, proper esd precautions should be followed to avoid exposing the device to discharges which may be detrimental to its performance. table 1. maximum ratings (maximum ratings are the limits to which the device can be exposed without ca using permanent damage.) rating symbol value unit maximum acceleration (all axes) g max 10,000 g analog supply voltage av dd -0.3 to +3.6 v digital i/o pins supply voltage dv dd_io -0.3 to +3.6 v drop test d drop 1.8 m storage temperature range t stg -40 to +125 c
sensors freescale semiconductor 3 MMA7450L table 2. operating characteristics unless otherwise noted: ?20c < t a < 65c, 2.4 v < av dd < 3.6 v, acceleration = 0g, loaded output characteristic symbol min typ max unit analog supply voltage standby operation mode enable bus mode digital i/o pins supply voltage standby operation mode enable bus mode av dd av dd dv dd_io dv dd_io 2.4 1.71 1.71 2.8 0 1.8 1.8 3.6 av dd 3.6 v v v v supply current drain (av dd /gnd) operation mode pulse detect function mode standby mode (except data loading and i 2 c/spi communication period) i dd i dd i dd ? ? ? 400 550 5 tbd tbd tbd a a a operating temperature range t a -20 25 +85 c acceleration range x-axis, y-axis, z-axis gfs gfs gfs 2 4 8 ? ? ? ? ? ? g g g output signal (t a =25c, av dd =2.8 v) zero g 2g range (25c) 8bit 4g range (25c) 8bit 8g range (25c) 8bit 8g range (25c) 10bit v off v off v off v off -16 -8 -4 -16 ? ? ? ? +16 +8 +4 +16 lsb lsb lsb lsb resolution (t a =25c, av dd =2.8 v) 2g range (25c) 8bit 4g range (25c) 8bit 8g range (25c) 8bit 8g range (25c) 10bit ? ? ? ? 15.6 31.2 62.4 15.6 ? ? ? ? mg mg mg mg sensitivity (t a =25c, av dd =2.8 v) 2g range (25c) 8bit 4g range (25c) 8bit 8g range (25c) 8bit 8g range (25c) 10bit v out v out v out v out ? ? ? ? 64 32 16 64 ? ? ? ? lsb/g lsb/g lsb/g lsb/g self test output response zout st z ?+64? lsb input high voltage input low voltage v ih v il 0.85dv dd _io -0.3v ? ? dv dd _io + 0.3 0.3dv dd _io psrr (av dd ) 0 to 20 khz 0 to 50 khz ? ? tbd tbd ? ? db db internal clock frequency t clk tbd 150 tbd khz spi frequency dv dd_io < 2.4 v dv dd_io > 2.4 v ? ? 4 8 ? ? mhz mhz output data rate (x, y, z set) ? 125 or 250 ? hz bandwidth for data measurement (user selectable) ? ? 62.5 125 ? ? hz hz
sensors 4 freescale semiconductor MMA7450L 1. these limits define the range of operation for which the part will meet specification. 2. within the supply range of 2.4 and 3.6 v, the device operates as a fully calibrated linear ac celerometer. beyond these suppl y limits the device may operate as a linear device but is not guaranteed to be in calibration. 3. this value is measured with g-select in 2g mode. 4. the device can measure both + and - acceleration. the output is at mid-supply with no accele ration. the output will increase above vdd/2 for positive acceleration. the output will decrease below vdd/2 for negative acceleration. 5. the response time is between 10% of full scale vdd i nput voltage and 90% of the final operating output voltage. 6. the response time is between 10% of full scale standby m ode input voltage and 90% of the final operating output voltage. 7. the response time is between 10% of the full scale self test input voltage and 90% of the self test output voltage. 8. a measure of the device ability to reject acceleration is applied 90 from the true axis of sensitivity. note: the response time is between 10% of full scale v dd input voltage and 90% of the final operating output voltage. control timing wait time for iic/spi ready after power on turn on response time (standby to normal mode) turn off response time (normal to standby mode) self test response time sensing element resonant frequency xy z internal sampling frequency t su t ru t rd t st f gcellxy f gcellz f clk 1 20 20 ms ms ms ms khz khz khz nonlinearity (2 g range) -1 ? +1 %fs cross axis sensitivity -5 +5 % orthogonality error of channels tbd tbd package to die misalignment 1 rf field influence to sensor tbd lsb table 3. function para meters for detection v l < v dd < v h ; t l < t a < t h unless otherwise specified characteristic symbol min typ max unit level detection detection threshold range 0 fs g pulse detection pulse detection range (adjustable range) 0.5 127 ms time step for pulse detection 0.5 ms threshold range for pulses 0 fs g detection levels for threshold (5) 127 levels latency timer (adjustable range) 1 150 ms time window (adjustable range) 1 250 ms measurement bandwidth for detecting interrupt 600 hz time step for latency timer and time window 1 ms table 2. operating characteristics (continued) unless otherwise noted: ?20c < t a < 65c, 2.4 v < av dd < 3.6 v, acceleration = 0g, loaded output characteristic symbol min typ max unit
sensors freescale semiconductor 5 MMA7450L principle of operation the freescale accelerometer is a surface-micromachined integrated-circuit accelerometer. the device consists of a surface micromachined capacitive sensing cell (g-cell) and a signal conditioning asic contained in a single package. the sensing element is sealed hermetically at the wafer level using a bulk micromachined cap wafer. the g-cell is a mechanical structure formed fr om semiconductor materials (polysilicon) using semiconductor processes (masking and etching). it can be modeled as a set of beams attached to a movable central mass that move between fixed beams. the movable beams can be deflected from their rest position by subjecting the system to an acceleration ( figure 3 ). as the beams attached to the central mass move, the distance from them to the fixed beams on one side will increase by the same amount that the distance to the fixed beams on the other side decreases. the change in distance is a measure of acceleration. the g-cell beams form two back-to-back capacitors ( figure 3 ). as the center beam moves with acceleration, the distance between the beams changes and each capacitor's value will change, (c = a /d). where a is the area of the beam, is the dielectric constant, and d is the distance between the beams. the asic uses switched capacitor techniques to measure the g-cell capacitors and extract the acceleration data from the difference between the two capacitors. the asic also signal conditions and filters (switched capaci tor) the signal, providing a high level digital output voltage that is ratiometric and proportional to acceleration. figure 3. simplified transducer physical model features self test the sensor provides a self te st feature that allows the verification of the mechanical a nd electrical integrity of the accelerometer at any time before or after installation. this feature is critical in applications such as hard disk drive protection where system integrity must be ensured over the life of the product. customers ca n use self test to verify the solderability to confirm that the part was mounted to the pcb correctly. to use this feature to verify the 0g-detect function, the accelerometer should be held upside down so that the z axis experiences -1g. when the se lf test function is initiated through the mode control register, accessing the ?self test? bit, an electrostatic force is app lied to each axis to cause it to deflect. the z-axis is trimmed to deflect 1g. this procedure assures that both the mechanical (g-cell) and electronic sections of the accelerometer are functioning. g-select the g-select feature enables the selection between 3 sensitivities for measurement. depending on the values in the mode control register ($16 ), the MMA7450L?s internal gain will be changed allowing it to function with a 2g, 4g or 8g measurement sensitivity. this feature is ideal when a product has applications requiring two or more sensitivities for optimum performance and for enabling multiple functions. the sensitivity can be changed during the operation by modifying the two glvl bits located in the mode control register. glvl [1:0] 00: 8g is selected for measurement range. 01: 2g is selected for measurement range. 10: 4g is selected for measurement range. standby mode this digital output 3-axis accelerometer provides a standby mode that is ideal fo r battery operated products. when standby mode is active, the device outputs are turned off, providing significant reduct ion of operating current. when the device is in standby mode the current will be reduced to 5 a typical. in standby mode the device can read and write to the registers with the i 2 c/spi available, but no new measurements can be taken in this mode as all current consuming parts are off. the mode of the device is controlled through the mode control register by accessing the two mode bits as shown in table 5 . measurement mode during measurement mode, continuous measurements on all three axes enabled. the g-range for 2g, 4g, or 8g are selectable with 8-bit data and the g-range of 8g is selectable with 10-bit data. the sample rate during measurement mode is 125 hz. therefore, when a conversion is complete (signaled by the drdy flag), the next measurement will be ready 8 ms later. acceleration $16: mode control register (read/write) d7 d6 d5 d4 d3 d2 d1 d0 bit -- drpd spi3w ston glvl[1] glvl[0] mode[1] mode[0] function 0 0 0 0 0 0 0 0 default table 4. g-select description g-select g-range sensitivity 00 8 g 16 lsb/g 01 2 g 64 lsb/g 10 4 g 32 lsb/g table 5. mode descriptions mode [0:1] function 00 standby mode 01 measurement mode 10 level detection mode 11 pulse detection mode
sensors 6 freescale semiconductor MMA7450L when measurements on all three axes are complete, a logic high level is output to the drdy pin, indicating ?measurement data is ready.? the drdy status can be monitored by the drdy bit in st atus register (address: $09). the drdy pin is kept high until one of the three output value registers are read. if the next measurement data is written before the previous data is read, the dovr bit in the status register will be set. also note that in measurement mode, level detection mode and pulse detection mode are not available. level detection mode level detection mode in level detection mode, the measurements for x, y and z are all enabled with 2g/4g and 8g range available.the detection of thresholds for an acceleration signal level for the combinations of x and y or x, y, and z is enabled. this is used for motion detection where the threshold can be user set depending on the application or us er specific requirements. when a motion event is detect ed, one of the interrupt pins (int1 or int2) will output a logic high output signaling the event is detected. setting for motion detection to configure the MMA7450L for motion detection, after all three axes are enabled for detection, set the ldpol bit in control register 2 (address: $19) to 0. when the output value of one of the enabled axes exceeds the threshold limit value, either int1 or int2 pin will output a logic high indicating the event was detected. ? if ldpol = 0 and all three axes are enabled for detection ? when the specified motion condition is detected, int1 or int2 will output a logic high ??xout threshold? or ?yout threshold? or ?zout threshold? threshold limit value is common for all three axes. positive/negative and absolute value option is available. assigning and clearing the interrupt pins int1/int2 pin assignment for level detection is controlled by control register 1 (address:$18). detection status is able to be monitored by detection source register (address:$0a). once the configured event is detected, int pin or register bi t will not be cleared until the respective clear bit (clrint1 or clrint2) in interrupt latch reset register (address: $17) is set. clrint1 and clrint2 should be cleared before starti ng next detection. otherwise, int pin or register will not set. note: measurement period and bandwidth for level detection is different fr om data output rate and the bandwidth of ?measurement.? please refer to functional parameter fo r detection for more information. pulse detection mode pulse detection mode in pulse detection mode, both 2g/4g and 8g range are available. measurements for x, y and z in 2g/4g or 8g mode are enabled. the level detection is also enabled in this mode. the pulse detected by the accele ration signal is enabled with single pulse and double pulse detection allowing the choice of either positive, negative or absolute value pulse detection. setting for motion detection for the pdpol bit in control register 2 (address: $19) the register should be set to ?0? for motion detection. when the output value of one of the enabled axes exceeds the threshold limit value, logic high level is output to int1 or int2 pin and indicates the event was detected. ? if pdpol = 0 and all three axes are enabled for detection ? when the condition below was detected, logic high level outputs to int1 or int2 ??xout threshold? or ?yout threshold? or ?zout threshold? setting for free fall detection to configure the MMA7450L for freefall detection, set the pdpol bit in control register 2 (address: $19) to 1. next, set the register for time window for 2nd pulse value (address $1e) to 0. when the output values of al l enabled axes are below the threshold limit continuously during the period specified in latency timer value register, logic high level is output to int1 or int2 pin indicati ng freefall was detected. filtering the 3 axis accelerometer contains digital filtering. intpin: 0:int1 will be used for event 1:int2 will be used for event
sensors freescale semiconductor 7 MMA7450L figure 4. single pulse detection figure 5. double pulse detection figure 6. negative pulse detection
sensors 8 freescale semiconductor MMA7450L digital interface the MMA7450L has both an i 2 c and spi digital output available for a communication in terface. when cs pin is used for slave select, spi communicat ion is selected. when cs is high, i 2 c communication is selected and spi is disabled. note: it is recommended to disable i 2 c during spi communication to avoid communication errors between devices using a different spi communication protocol. to disable i 2 c, set the i 2 cdis bit in i 2 c device address register using spi. i 2 c slave interface i 2 c is a synchronous serial communication between a master device and one or more slave devices. the master is typically a microcontroller, which provides the serial clock signal and addresses the slave device(s) on the bus. the MMA7450L communicates only in slave operation where the device address is $1d. multiple read and write modes are available. the protocol supports slave only operation. it does not support hs mode, ?10-bit addressing?, ?general call? and :?start byte?. single byte read the MMA7450L has an 8-bit adc that can sample, convert and return sensor data on request. the transmission of an 8-bit command begins on the falling edge of scl. after the eight clock cycles are used to send the command, note that the data returned is sent with the msb first once the data is received. figure 7 shows the timing diagram for the accelerometer 8-bit i 2 c read operation. the master (or mcu) transmits a start condition (s) to the MMA7450L, slave address ($1d), with the r/w bit set to ?0? for a write, and the MMA7450L sends an acknowledgement. then the master (or mcu) transmits the 8-bit address of the register to read and the MMA7450L sends an acknowledgement. the master (or mcu) transmits a repeated start condition (sr) and then addresses the MMA7450L ($1d) with the r/w bit set to ?1? for a read from the previously sele cted register. the slave then acknowledges and transmits the data from the requested register. the master does not acknowledge (nack) it received the transmitted data, but transmits a stop condition to end the data transfer. figure 7. single byte read - the master is reading one address from the MMA7450L multiple bytes read the MMA7450L automatically increments the received register address commands after a read command is received. therefore, after following the steps of a single byte read, multiple bytes of data can be read from sequential registers after each MMA7450L acknowledgment (ack) is received until a nack is rece ived from the master followed by a stop condition (sp) signalling an end of transmission. see figure 8 . figure 8. multiple bytes read - the master is reading multiple sequential registers from the MMA7450L single byte write to start a write command, the master transmits a start condition (st) to the MMA7450L, slave address ($1d) with the r/w bit set to ?0? for a write, the MMA7450L sends an acknowledgement. then the master (mcu) transmits the 8- bit address of the register to write to, and the MMA7450L sends an acknowledgement. then the master (or mcu) transmits the 8-bit data to write to the designated register and the MMA7450L sends an acknowledgement that it has received the data. since this transmission is complete, the master transmits a stop conditio n (sp) to the data transfer. the data sent to the MMA7450L is now stored in the appropriate register. see figure 9 . figure 9. single byte write - the master (mcu) is writing to a single register of the MMA7450L multiple bytes write the MMA7450L automatically increments the received register address commands after a write command is received. therefore, after follow ing the steps of a single byte write, multiple bytes of data can be written to sequential registers after each MMA7450L acknowledgment (ack) is received. see figure 10 . figure 10. multiple byte writ es - the master (mcu) is writing to multiple sequential registers of the MMA7450L spi slave interface the MMA7450L also uses serial peripheral interface communication as a digital communication. the spi communication is primarily used for synchronous serial communication between a master device and one or more slave devices. see figure 16 for an example of how to configure one master wit h two MMA7450L devices. the MMA7450L is always operated as a slave device. typically, the master device would be a microcontroller which would drive the clock (spc) and ch ip select (cs) signals. the spi interface consists of two control lines and two data lines: cs, spc, sdi, and sdo. the cs, also known as chip select, is the slave device enable which is controlled by the spi master. cs is driven low at the start of a transmission. cs
sensors freescale semiconductor 9 MMA7450L is then driven high at the end of a transmission. spc is the serial port clock which is also controlled by the spi master. sdi and sdo are the serial port data input and the serial port data output. the sdi and sdo data lines are driven at the falling edge of the spc and should be captured at the rising edge of the spc. read and write register commands are completed in 16 clock pulses or in multiples of 8, in the case of a multiple byte read/write. spi read operation a spi read transfer consists of a 1-bit read/write signal, a 6-bit address, and 1-bit don?t care bit. (1-bit r/w=0 + 6-bits address + 1-bit don?t care). the data to read is sent by the spi interface during the next transfer. see figure 11 and figure 12 for the timing diagram for an 8-bit read in 4 wire and 3 wire modes, respectively. figure 11. spi timing diagram for 8-bit register read (4 wire mode) figure 12. spi timing diagram for 8-bit register read (3 wire mode) spi write operation in order to write to one of t he 8-bit registers, an 8-bit write command must be sent to the MMA7450L. the write command consists of an msb (0=read, 1=write) to indicate writing to the MMA7450L register, followed by a 6-bit address and 1 don?t care bit. the command should then be followed the 8-bit data transfer. see figure 13 for the timing di agram for an 8-bit data write. figure 13. spi timing diagram for 8-bit register write (3 wire mode)
sensors 10 freescale semiconductor MMA7450L basic connections pin descriptions figure 14. pinout description recommended pcb layout for interfacing accelerometer to microcontroller figure 15. i 2 c connection to mcu figure 16. spi connection to mcu notes: 1. use 100 nf capacitor on v dd to decouple the power source. 2. physical coupling distance of the accelerometer to the microcontroller should be minimal. 3. place a ground plane beneath the accelerometer to reduce noise, the ground pl ane should be attached to all of the open ended terminals shown in figure 15 and figure 16 . 4. pcb layout of power and ground should not couple power supply noise. 5. accelerometer and microcontroller should not be a high current path. 6. any external power supply switching frequency should be selected such that they do not interfere with the internal accelerometer sampling frequency (sampling frequency). this will prevent aliasing errors. table 6. pin descriptions pin no. pin name description 1 dvdd_io digital power supply for i/o pads 3, 10, 11 nc no connection or connect to gnd 4 iaddr0 i 2 c address bit 0 (optional) 2, 5 gnd ground 6 avdd analog power supply (main power supply) 7cs spi enable, i 2 c/spi mode selection (1:1 2 c, 0:spi enabled) 8 int1/drdy interrupt1 / data ready 9 int2 interrupt2 12 sdo spi serial data output 13 sda/sdi/ sdo i 2 c serial data (sda), spi serial data input (sdi), 3-wire interface serial data output (sdo) 14 scl/spc i 2 c serial clock (scl), spi serial clock (spc) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 avdd gnd dvdd_io slc/spc cs int1/drdy int2 n/c sdo sda/sdi/sdo n/c n/c n/c gnd top view 100uf 100uf 100uf 100uf
sensors freescale semiconductor 11 MMA7450L table 7. user register summary address name definition bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00 xoutl 10 bits output value x lsb xout[7] xout[6] xout[5] xout[4] xout[3] xout[2] xout[1] xout[0] $01 xouth 10 bits output value x msb -- -- -- -- -- -- xout[9] xout[8] $02 youtl 10 bits output value y lsb yout[7] yout[6] yout[5] yout[4] yout[3] yout[2] yout[1] yout[0] $03 youth 10 bits output value y msb -- -- -- -- -- -- yout[9] yout[8] $04 zoutl 10 bits output value z lsb zout[7] zout[6] zout[5] zout[4] zout[3] zout[2] zout[1] zout[0] $05 zouth 10 bits output value z msb -- -- -- -- -- -- zout[9] zout[8] $06 xout8 8 bits output value x xout[7] xout[6] xout[5] xout[4] xout[3] xout[2] xout[1] xout[0] $07 yout8 8 bits output value y yout[7] yout[6] yout[5] yout[4] yout[3] yout[2] yout[1] yout[0] $08 zout8 8 bits output value z zout[7] zout[6] zout[5] zout[4] zout[3] zout[2] zout[1] zout[0] $09 status status registers -- -- -- -- -- perr dovr drdy $0a detsrc detection source registers ldx ldy ldz pdx pdy pdz int1 int2 $0b tout ?temperature output value? (optional) tmp[7] tmp[6] tmp[5] tmp[4] tmp[3] tmp[2] tmp[1] tmp[0] $0c (reserved) -- -- -- -- -- -- -- -- $0d i2cad i2c device address i2cdis dad[6] dad[5] dad[4] dad[3] dad[2] dad[1] dad[0] $0e usrinf user information (optional) ui[7] ui[6] ui[5] ui[4] ui[3] ui[2] ui[1] ui[0] $0f whoami ?who am i? value (optional) id[7] id[6] id[5] id[4] id[3] id[2] id[1] id[0] $10 xoffl offset drift x value (lsb) xoff[7] xoff[6] xoff[5] xoff[4] xoff[3] xoff[2] xoff[1] xoff[0] $11 xoffh offset drift x value (msb) -- -- -- -- -- xoff[10] xoff[9] xoff[8] $12 yoffl offset drift y value (lsb) yoff[7] yoff[6] yoff[5] yoff[4] yoff[3] yoff[2] yoff[1] yoff[0] $13 yoffh offset drift y value (msb) -- -- -- -- -- yoff[10] yoff[9] yoff[8] $14 zoffl offset drift z value (lsb) zoff[7] zoff[6] zoff[5] zoff[4] zoff[3] zoff[2] zoff[1] zoff[0] $15 zoffh offset drift z value (msb) -- -- -- -- -- zoff[10] zoff[9] zoff[8] $16 mctl mode control lpen drpd spi3w ston glvl[1] glvl[0] mod[1] mod[0] $17 intrst interrupt latch reset -- -- -- -- -- -- clrint2 clrint1 $18 ctl1 control 1 -- thopt zda yda xda intrg[1] intrg[0] intpin $19 ctl2 control 2 -- -- -- -- -- drvo pdpl ldpl $1a ldth level detection threshold limit value ldth[7] ldth[6] ldth[5] ldth[4] ldth[3] ldth[2] ldth[1] ldth[0] $1b pdth pulse detection threshold limit value pdth[7] pdth[6] pdth[5] pdth[4] pdth[3] pdth[2] pdth[1] pdth[0] $1c pw pulse duration value pd[7] pd[6] pd[5] pd[4] pd[3] pd[2] pd[1] pd[0] $1d lt latency time value lt[7] lt[6] lt[5] lt[4] lt[3] lt[2] lt[1] lt[0] $1e tw time window for 2 nd pulse value tw[7] tw[6] tw[5] tw[4] tw[3] tw[2] tw[1] tw[0] $1f (reserved) -- -- -- -- -- -- -- --
sensors 12 freescale semiconductor MMA7450L register definitions signed byte data (2?s compliment): zero g = 10?h000 reading low byte xoutl latches high byte xouth to allow 10-bit reads. xouth should be read directly following xoutl read. signed byte data (2?s compliment): zero g = 10?h000 reading low byte xoutl latches high byte xouth to allow 10-bit reads. xouth should be read directly following xoutl read. signed byte data (2?s compliment): zero g = 10?h000 reading low byte youtl latches high byte youth to allow coherent 10-bit reads. youth should be read directly following youtl. signed byte data (2?s compliment): zero g = 10?h000 reading low byte zoutl latches high byte zouth to allow coherent 10-bit reads. zouth should be read directly following zoutl. signed byte data (2?s compliment): zero g = 10?h000 reading low byte zoutl latches high byte zouth to allow coherent 10-bit reads. zouth should be read directly following zoutl. signed byte data (2?s compliment): zero g = 8?h00 $00 : 10bits output value x lsb (read only) d7 d6 d5 d4 d3 d2 d1 d0 bit xout [7] xout [6] xout [5] xout [4] xout [3] xout [2] xout [1] xout[0] function 0 0 0 0 0 0 0 0 default $01 : 10bits output value x msb (read only) d7 d6 d5 d4 d3 d2 d1 d0 bit -- -- -- -- -- -- xout [9] xout[8] function 0 0 0 0 0 0 0 0 default $02 : 10bits output value y lsb (read only) d7 d6 d5 d4 d3 d2 d1 d0 bit yout [7] yout [6] yout [5] yout [4] yout [3] yout [2] yout [1] yout[0] function 0 0 0 0 0 0 0 0 default $03 : 10bits output value y msb (read only) d7 d6 d5 d4 d3 d2 d1 d0 bit -- -- -- -- -- -- yout [9] yout[8] function 0 0 0 0 0 0 0 0 default $04 : 10bits output value z lsb (read only) d7 d6 d5 d4 d3 d2 d1 d0 bit zout [7] zout [6] zout [5] zout [4] zout [3] zout [2] zout [1] zout[0] function 0 0 0 0 0 0 0 0 default $05 : 10bits output value x msb (read only) d7 d6 d5 d4 d3 d2 d1 d0 bit -- -- -- -- -- -- zout [9] zout[8] function 0 0 0 0 0 0 0 0 default $06: 8bits output value x (read only) d7 d6 d5 d4 d3 d2 d1 d0 bit xout[7] xout [6] xout [5] xout [4] xout [3] xout [2] xout [1] xout [0] function 0 0 0 0 0 0 0 0 default
sensors freescale semiconductor 13 MMA7450L signed byte data (2?s compliment): zero g = 8?h00 signed byte data (2?s compliment): zero g = 8?h00 drdy 1: data is ready 0: data is not ready dovr 1: data is over written 0: data is not over written perr 1: parity error is de tected in trim data. then, self test is disabled 0: parity error is not detected in trim data ldx 1: level detection detected on x axis 0: level detection not detected on x axis ldy 1: level detection detected on y axis 0: level detection not detected on y axis ldz 1: level detection detected on z axis 0: level detection not detected on z axis pdx *note 1: pulse is detected on x axis at single pulse detection 0: pulse is not detected on x axis at single pulse detection pdy *note 1: pulse is detected on y axis at single pulse detection 0: pulse is not detected on y axis at single pulse detection pdz *note 1: pulse is detected on z axis at single pulse detection 0: pulse is not detected on z axis at single pulse detection note: this bit value is not valid at double pulse detection int1 1: interrupt assigned by ?detection control? register is de- tected 0: interrupt assigned by ?detection control? register is not detected int2 1: interrupt assigned by ?detection control? register is de- tected 0: interrupt assigned by ?detection control? register is not detected i2cdis 0: i2c and spi are available. 1: i2c is disabled. dvad[6:0]: i2c device address $07: 8bits output value y (read only) d7 d6 d5 d4 d3 d2 d1 d0 bit yout[7] yout [6] yout [5] yout [4] yout [3] yout [2] yout [1] yout [0] function 0 0 0 0 0 0 0 0 default $08: 8bits output value z (read only) d7 d6 d5 d4 d3 d2 d1 d0 bit zout[7] zout [6] zout [5] zout [4] zout [3] zout [2] zout [1] zout [0] function 0 0 0 0 0 0 0 0 default $09: status register (read only) d7 d6 d5 d4 d3 d2 d1 d0 bit -- -- -- -- -- perr dovr drdy function 0 0 0 0 0 0 0 0 default $0a: detection source register (read only) d7 d6 d5 d4 d3 d2 d1 d0 bit ldx ldy ldz pdx pdy pdz int2 int1 function 0 0 0 0 0 0 0 0 default $0d: i2c device address (bit 6-0: read only, bit 7: read/write) d7 d6 d5 d4 d3 d2 d1 d0 bit i2cdis dvad[6] dvad[5] dvad[4] dvad[3] dvad[2] dvad[1] dvad[0] function 0 0 0 1 1 1 0 1 default
sensors 14 freescale semiconductor MMA7450L ui2[7:0]: user information signed byte data (2?s compliment): user level offset trim value for x axis *note: bit weight is for 2g 8bit data output. typical value for refere nce only. variation is specified in ?electrical characteristics ? section. signed byte data (2?s compliment): user level offset trim value for x axis signed byte data (2?s compliment): user level offset trim value for y axis *note: bit weight is for 2g 8bit data output. typical value for refere nce only. variation is specified in ?electrical characteristics ? section. signed byte data (2?s compliment): user level offset trim value for y axis *note: bit weight is for 2g 8bit data output. typical value for refere nce only. variation is specified in ?electrical characteristics ? section. $0e: user information (read only: optional) d7 d6 d5 d4 d3 d2 d1 d0 bit ui[7] ui[6] ui[5] ui[4] ui[3] ui[2] ui[1] ui[0] function 0/otp 0/otp 0/otp 0/otp 0/otp 0/otp 0/otp 0/otp default $0f: ?who am i? value (read only: optional) d7 d6 d5 d4 d3 d2 d1 d0 bit id[7] id [6] id [5] id [4] id [3] id [2] id [1] id [0] function 0/otp 0/otp 0/otp 0/otp 0/otp 0/otp 0/otp 0/otp default $10: offset drift x lsb (read/write) d7 d6 d5 d4 d3 d2 d1 d0 bit xoff[7] xoff [6] xoff [5] xoff [4] xoff [3] xoff [2] xoff [1] xoff [0] function 0 0 0 0 0 0 0 0 default bit xoff[7] xoff[6] xoff[5] xoff[4] xoff[3] xoff[2] xoff[1] xoff[0] weight (*note) 64 lsb 32 lsb 16 lsb 8 lsb 4 lsb 2 lsb 1 lsb 0.5 lsb $11: offset drift x msb (read/write) d7 d6 d5 d4 d3 d2 d1 d0 bit -- -- -- -- -- xoff [10] xoff [9] xoff [8] function 0 0 0 0 0 0 0 0 default $12: offset drift y lsb (read/write) d7 d6 d5 d4 d3 d2 d1 d0 bit yoff[7] yoff [6] yoff [5] yoff [4] yoff [3] yoff [2] yoff [1] yoff [0] function 0 0 0 0 0 0 0 0 default bit yoff[7] yoff[6] yoff[5] yoff[4] yoff[3] yoff[2] yoff[1] yoff[0] weight (*note) 64 lsb 32 lsb 16 lsb 8 lsb 4 lsb 2 lsb 1 lsb 0.5 lsb $13: offset drift y msb (read/write) d7 d6 d5 d4 d3 d2 d1 d0 bit -- -- -- -- -- yoff [10] yoff [9] yoff [8] function 0 0 0 0 0 0 0 0 default bit yoff[10] yoff[9] yoff[8] weight (*note) polarity 256 lsb 128 lsb
sensors freescale semiconductor 15 MMA7450L signed byte data (2?s compliment): user level offset trim value for z axis *note: bit weight is for 2g 8bit data output. typical value for refere nce only. variation is specified in ?electrical characteristics ? section. signed byte data (2?s compliment): user level offset trim value for z axis *note: bit weight is for 2g 8bit data output. typical value for refere nce only. variation is specified in ?electrical characteristics ? section. glvl [1:0] 00: 8g is selected for measurement range. detection is 8g range. 01: 2g is selected for measurement range. detection is 8g range. 10: 4g is selected for measurement range. detection is 8g range. ston 0: self test is not enabled 1: self test is enabled spi3w 0: spi is 4 wire mode 1: spi is 3 wire mode drpd 0: data ready status is output to int1/drdy pin 1: data ready status is not output to int1/drdy pin $14: offset drift z lsb (read/write) d7 d6 d5 d4 d3 d2 d1 d0 bit zoff[7] zoff[6] zoff[5] zoff[4] zoff[3] zoff[2] zoff[1] zoff[0] function 0 0 0 0 0 0 0 0 default bit zoff[7] zoff[6] zoff[5] zoff[4] zoff[3] zoff[2] zoff[1] zoff[0] weight (*note) 64 lsb 32 lsb 16 lsb 8 lsb 4 lsb 2 lsb 1 lsb 0.5 lsb $15: offset drift z msb (read/write) d7 d6 d5 d4 d3 d2 d1 d0 bit -- -- -- -- -- zoff[10] zoff[9] zoff[8] function 0 0 0 0 0 0 0 0 default bit zoff[10] zoff[9] zoff[8] weight (*note) polarity 256 lsb 128 lsb $16: mode control register (read/write) d7 d6 d5 d4 d3 d2 d1 d0 bit -- drpd spi3w ston glvl[1] glvl[0] mode[1] mode[0] function 0 0 0 0 0 0 0 0 default mode[1:0] function 00 standby mode 01 measurement mode 10 level detection mode 11 pulse detection mode
sensors 16 freescale semiconductor MMA7450L clr_int1 1: clear ?int1? and ldx/ldy/ldz or pdx/pdy/pdz bits in ?detection source? register depending on ?detection control? reg- ister setting. 0: do not clear ?int1? ldx/ldy/ldz or pdx/pd y/pdz bits in ?detection source? register. clr_int2 1: clear ?int2? and ldx/ldy/ldz or pdx/pdy/pdz bits in ?detection source? register depending on ?detection control? reg- ister setting. 0: do not clear ?int2? and ldx/ ldy/ldz or pdx/pdy/pdz bits in ?detection source? register. intpin 0: int1 pin is routed to ?int1? register and int2 pin is routed to ?int2? register. 1: int2 pin is routed to ?int1? register and int1 pin is routed to ?int2? register. note: assigned to single pulse detection even if double pulse detection is selected. ?double pulse detection se- lected? means ?time window for 2 nd pulse? is not equal zero. when double pulse detection is selected, int1 reg- ister bit is not able to be cleared by setting clr_int1 bit. it?s cleared by setting clr_int2 bit. in this case, setting clr_int2 clears both int1 and int2 register bits and re- set detecting operation itself. xda 1: x axis is disabled for detection. 0: x axis is enabled for detection. yda 1: y axis is disabled for detection. 0: y axis is enabled for detection. zda 1: z axis is disabled for detection. 0: z axis is enabled for detection. thopt (this bit is valid for level detection only, not valid for pulse detection) 0: threshold value is absolute only 1: positive/negative threshold value is available. dfbw 0: digital filter band width is 62.5 hz 1: digital filter band width is 125 hz ldpol 0: level detection polarity is positive and detecting condi- tion is or 3 axes. 1: level detection polarity is negative detecting condition is and 3 axes. pdpol 0: pulse detection polarity is positive and detecting condi- tion is or 3 axes. 1: pulse detection polarity is negative and detecting con- dition is and 3 axes. drvo 0: standard drive st rength on sda/sdo pin 1: strong drive strength on sda/sdo pin $17: interrupt latc h reset (read/write d7 d6 d5 d4 d3 d2 d1 d0 bit -- -- -- -- -- -- clr_int2 clr_int1 function 0 0 0 0 0 0 0 0 default $18: control 1 (read/write) d7 d6 d5 d4 d3 d2 d1 d0 bit dfbw thopt zda yda xda intreg[1] intreg[0] intpin function 0 0 0 0 0 0 0 0 default intreg[1:0] ?int1? register bit ?int2? register bit 00 level detection pulse detection 01 pulse detection level detection 10 single pulse detection (*note) pulse detection $19: control 2 (read/write) d7 d6 d5 d4 d3 d2 d1 d0 bit -- -- -- -- -- drvo pdpl ldpl function 0 0 0 0 0 0 0 0 default
sensors freescale semiconductor 17 MMA7450L ldth[7:0]: level detection threshold value. if thopt bit in detection control register is ?0?, it is unsigned 7 bits value and ldth[7] should be ?0?. if thopt bit is ?1?, it is signed 8 bits value. pdth[6:0]: pulse detection threshold value (unsigned 7 bits). xpdth: this bit should be ?0?. min: pd[7:0] = 4?h01 = 0.5 ms max: pd[7:0] = 4?hff = 127 ms 1 lsb = 0.5 ms min: lt[7:0] = 8?h01 = 1 ms max: lt[7:0] = 8?hff = 255 ms 1 lsb = 1 ms min: tw[7:0] = 8?h01 = 0 ms (single pulse detection) max: tw[7:0] = 8?hff = 255 ms 1 lsb = 1 ms $1a: level detection threshold limit value (read/write) d7 d6 d5 d4 d3 d2 d1 d0 bit ldth[7] ldth[6] ldth[5] ldth[4] ldth[3] ldth[2] ldth[1] ldth[0] function 0 0 0 0 0 0 0 0 default $1b: pulse detection threshold limit value (read/write) d7 d6 d5 d4 d3 d2 d1 d0 bit xpdth pdth[6] pdth[5] pdth[4] pdth[3] pdth[2] pdth[1] pdth[0] function 0 0 0 0 0 0 0 0 default $1c: pulse duration value (read/write) d7 d6 d5 d4 d3 d2 d1 d0 bit pd[7] pd[6] pd[5] pd[4] pd[3] pd[2] pd[1] pd[0] function 0 0 0 0 0 0 0 1 default $1d: latency time value (read/write) d7 d6 d5 d4 d3 d2 d1 d0 bit lt[7] lt[6] lt[5] lt[4] lt[3] lt[2] lt[1] lt[0] function 0 0 0 0 0 0 0 1 default $1e: time window for 2nd pulse value (read/write) d7 d6 d5 d4 d3 d2 d1 d0 bit tw[7] tw[6] tw[5] tw[4] tw[3] tw[2] tw[1] tw[0] function 0 0 0 0 0 0 0 0 default
sensors 18 freescale semiconductor MMA7450L sensing direction and output response the following figure shows sensing direction and the output response for 2g mode. figure 17. sensing direction and output response at 2g mode table 8. acceleration vs. output fs mode acceleration output 2g mode -2g $80 -1g $c1 0g $00 +1g $3f +2g $7f 4g mode -4g $80 -1g $e1 0g $00 +1g $1f +4g $7f 8g mode -8g $80 -1g $f1 0g $00 +1g $0f +8g $7f side view x out @0g=$00 y out @ +1g = $3f z out @0g=$00 x out @ +1g = $3f y out @0g=$00 z out @0g=$00 x out @ -1g = $c1 y out @0g=$00 z out @ 0g = $00 1 65432 13 12 11 10 9 8 14 7 x out @0g=$00 y out @ -1g = $c1 z out @0g=$00 direction of earth's gravity field.* top view x out @0g=$00 y out @0g=$00 z out @ -1g = $c1 x out @0g=$00 y out @0g=$00 z out @ +1g = $3f 1 65432 13 12 11 10 9 8 14 7 16 5 4 3 2 13 12 11 10 9 8 14 7 1 65432 13 12 11 10 9 8 14 7 to p to p bottom bottom * when positioned as shown, the earth?s grav ity will result in a positive 1g output.
sensors freescale semiconductor 19 MMA7450L minimum recommended footprint for surface mounted applications surface mount board layout is a critical portion of the total design. the footprint for the surface mount packages must be the correct size to ensure proper solder connection interface between the board and the package. with the correct footprint, the packages will self-align when subjected to a solder reflow process. it is always recommended to design boards with a solder mask layer to avoid bridging and shorting between solder pads.
sensors 20 freescale semiconductor MMA7450L package dimensions case 1935-01 issue 0 14-lead lga
sensors freescale semiconductor 21 MMA7450L package dimensions case 1935-01 issue 0 14-lead lga
MMA7450L rev. 0 6/2007 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor lite rature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the application or use of any product or circuit, and specifically discl aims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale se miconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the fa ilure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemni fy and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2007. all rights reserved. rohs-compliant and/or pb-free versions of freesc ale products have the functi onality and electrical characteristics of their non-rohs-compliant and/or non-pb-free counterparts. for further information, see http:/www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp.

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